The implemented versions are all based on the sequential implementation from Correia [26] and are the following: (a) distributed, supported by a cluster of computers; (b) parallel, supported by a shared memory multiprocessor; (c) hybrid, supported by a cluster of multiprocessors.
For the sequential implementation on FPGA platform, the proposed hardware architecture has been implemented on a Xilinx Virtex-6 ML605 FPGA.
Fig. 14 Map-Reduce vs. sequential implementation.
The full sequential implementation of this cascade is proposed in Figure 7. Figure 7 Sequential implementation.
Compared to the sequential implementation, we found no influence of the parallelization on simulation results.
However, this test used a sequential implementation to mimic ESTCP test conditions.
We compared the Hadoop implementation against a sequential implementation that is executed on the same machine.
Therefore, a parallel implementation iterates through the grid in the same way as a sequential implementation.
The MIC implementation is compared with GPU, CPU and sequential implementation.
This has a time complexity of O(N log N) in its sequential implementation.
First results obtained from a sequential implementation, have shown that the latency time was too important.
