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Thread divergence and uncoalesced memory accesses are considered in the optimization process.

The L2 unified memory accesses are considered via handling the L1 data and program cache misses.

We register a hook to the virtual machine page fault event (EPT violations), which is raised when virtual machine memory accesses are denied.

In the second phase, called address translation, the addresses used by peripheral memory accesses are translated by DMAR, before crossing the host bridge (Fig. 1).

In the GPU implementation, all nodes in one subdomain lie within one pitch so that the memory accesses are aligned for both the synchronisation and the computation kernels.

We have observed that over 70% of simultaneous memory accesses are either the same for all the threads, or are affine expressions of the thread identifier.

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For this benchmark, 90% of the memory accesses were predicted precisely.

NoC platforms feature a growing amount of on-chip memory, and the cost of on-chip memory accesses is also smaller with respect to off-chip memories.

Using this one-dimensional address arrangement, the number of memory accesses is minimized in all of the operations of check node updates, bit node updates, initialization, and parity checks.

In order to appreciate the complexity of the two iterative modes, an accurate evaluation of the complexity in terms of number and type of operations and memory accesses is required.

However, it should be noted that the number of required memory access are much less than the arithmetic operations.

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