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Secondly, a heuristic based voltage assignment method is presented for accuracy and execution time trade-off.
Thirdly, different from previous works which do voltage assignment without physical information feedback, an inner loop is built between voltage assignment and LS placement under the constraints of both timing and physical layout.
The leakage reduction is done via simultaneous supply voltage selection, multiple threshold voltage assignment and template sizing.
We propose a novel microarchitecture aware gate sizing and threshold voltage assignment algorithm to mitigate this current limitation.
In this work, GPU-based parallel computing techniques is proposed for simultaneous gate sizing and threshold voltage assignment.
To realize MSV implementation, procedures such as voltage assignment, voltage island partitioning and level shifters (LSs) placement should be considered simultaneously during the floorplanning stage.
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This paper presents a novel sensitivity-based, transistor-level, dual threshold voltage (Vth) assignment technique for the design of low power nanoscale CMOS circuits.
We optimize the circuit power using two major approaches, pipelining and dual-supply voltage (dual-Vdd) assignment.
Thereafter, the SRAM cell is subjected to a dual threshold voltage (dual-VTh) assignment based on a novel statistical Design of Experiments–Integer Linear Programming (DOE ILP) approach.
To attack the second problem, we first design an algorithm based on the earliest time first scheduling to determine the application's finish time if a voltage and frequency assignment is given; then, we develop a genetic algorithm to search the solution space for the voltage and frequency assignment that minimizes the overall system energy consumption and meets the application's deadline.
To improve power efficiency, we have designed a new pipelining to reduce the number of gates need to be assigned to the high supply voltage when combined with the dual-Vdd assignment.
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