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Non-volatile logic is a viable solution to overcome the leakage power issue which has become a major obstacle to CMOS technology scaling.
This technology is currently being pursued not only for scalable non-volatile spin-transfer-torque magnetoresistive random access memory, but also for various forms of non-volatile logic (Spin-Logic).
Thus, an intrinsic non-volatile logic-in-memory architecture can be realized.
This work proposes current- and voltage-controlled MTJ-based implication (IMP) logic gtes for future non-volatile logic-in-memory architecture.
Electric field control of ferromagnetism was so far demonstrated in a field effect transistor (FET) structure which have been used for non-volatile spin logic devices via carrier-mediated effect [9, 14].
A novel 4T2R STI-RRAM-based non-volatile SRAM fully logic compatible to CMOS logic process has been successfully demonstrated in pure CMOS logic process at 40 nm technology node without extra masks or steps.
13, 14 Current development of efficient spintronic devices is focused on exploiting the STT phenomenon for non-volatile memory and logic devices.
It is expected that CBRAM devices have very good opportunity for scaled (<11 nm technology node) non-volatile memory devices or logic gate operations.
These superior characteristics make STI-RRAM-based nv-SRAM a promising solution for low-power/high-speed logic non-volatile memory applications in the future.
This work opens up a way in designing multi-functional memristive devices, which could be an ideal solution for the neuromorphic computation, non-volatile information storage and logic operation.
Dodecane was also one of the 12 candidate volatiles identified by fuzzy logic analysis.
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