Sentence examples for vector width from inspiring English sources

Data collected from simulations of four reactor problems using OpenMC was then used in conjunction with the models to calculate the speedup due to vectorization as a function of the size of the particle bank and the vector width.

While the amount of DLP varies between applications of the same domain or even within a single application, processor architectures usually support a single vector width.

The core principles of this chapter apply to competing CPU and GPU architectures, but significant differences in performance can easily arise from variation in vector width, variations in thread context management, and instruction scheduling.

The first implementation of the architecture in CMOS065 technology features a vector width of 8 elements of 16 bit, is clocked at 250 MHz, and takes up 2.09.

This matches our expectations, because the parallelization granularity on the CPU is as small as the vector width, which is 4. On the GPU this granularity is much higher, as presented in Figure 7(b), here we see bands of different color every 256 particles.

This paper proposes the use of heterogeneous vector widths and a method to explore the heterogeneous vector widths for VLIW ASIPs.

In our context, heterogeneity corresponds to the usage of two or more different vector widths in a single ASIP.

After a brief explanation of the target ASIP architecture model, the paper describes the vector-width exploration method and explains the associated design automation tools.

The basic control algorithm is based on Field Oriented Control (FOC) with space vector pulse width modulation (SVPWM) technique.

The behavior of the proposed system has been successfully compared with another one with multilevel space vector pulse width modulation.

A standard three-level space vector pulse width modulation (SVPWM) by nearest three vectors (NTVs) approach is adopted to regulate each couple of VSIs.