Sentence examples for using a single implementation from inspiring English sources
Missing data for deprivation (19%) were due to a computer error during data collection, and so are assumed to be missing completely at random and were imputed by using a single implementation of the ICE procedure [ 23].
In this comparison, we used the full pipeline proposed in Section 3 using a single core CPU implementation of the IIR filter.
Our results show that parallel implementation achieves typical acceleration values in the order of 80 120 times compared to CPU using a single-threaded implementation on a 2.33 GHz desktop computer.
In sequential mode, the actual coordination of Map and Reduce jobs is done locally on a single machine using a single-thread implementation of MapReduce: the data source is fed tuple by tuple to the mapper, the output tuples are collected, split according to their keys, and each list is sent to the reducer, again in a sequential fashion.
The performances have been evaluated and compared with another implementation using a single CPU node.
By distributing the workload between multiple CUDA-enabled GPUs and multicore processors, accelerations as high as 1000 × for PRISM and 15 × for multislice are achieved relative to traditional multislice implementations using a single 4-GPU machine.
In our tests, the GPU-based implementations using a single GPU device achieve >15 times speedup in forward modeling, and about 12 times speedup in gradient calculation, compared with the eight-core CPU implementations optimized by OpenMP.
To demonstrate the practical hardware feasibility, a specific architecture has been designed and its implementation has been carried out using a single FPGA chip.
In the next section, our specific design and implementation of a hybrid DS/FFH radio transceiver using a single FPGA are presented.
Furthermore, the current implementation completes the assembly in 1 day using a single CPU thread.
We also present our efforts toward exploring the design, implementation, and evaluation of a hybrid DS/FFH radio transceiver using a single field-programmable gate array (FPGA).
