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Another aspect which distinguishes SODA from other processor centered architectures is the use of scratchpad memory.
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A multicore FPGA platform with cache-integrated network interfaces (NIs) has been developed, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches (using implicit communication) and the efficiency of scratchpad memories (using explicit communication).
Data locality is exploited in Pattern Memory Units using banked scratchpad memories and configurable address decoders.
In this paper, we show how to leverage the structure and semantics of a dataflow model to make optimal use of scratchpads.
The PAMS supports static and dynamic data structures using descriptors and specialized scratchpad memory.
The control of the cache locking [52] and the allocation of data in the scratchpad memory [53, 54] can be optimized for the WCET.
Therefore, this experiment does not make use of the shared memory to reduce memory bandwidth bottleneck.
Furthermore, the integration of a program or compiler managed scratchpad memory can help to tighten bounds for hard-to-analyze memory access patterns.
In this report we present methods for scratchpad memory allocation of block diagram programs composed under the Heterochronous Dataflow (HDF) model of computation.
memory_object_init - Inform a memory manager on first use of a memory object.
This paper presents a novel scratchpad memory architecture that is used accelerate MapReduce applications by indexing and processing the key/value pairs.
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