In order to achieve both goals, a couple of different approaches have been considered to devise this type of architectures.
The dimension and complexity of this type of architectures are only acceptable for short to medium length LDPC codes.
Moreover, the reduction in the hardware cost also contributes to decrease the power consumption associated with this type of architectures.
To fully exploit this type of architectures, one needs to automatically determine how to partition the workload between both devices.
On the negative side, FPGAs are difficult to program and there is currently a lack of efficient implementations of a full spectral unmixing chain for hyperspectral image processing in these type of architectures.
For the type of architectures considered in our work, i.e. multi-core processors, an appealing property of these libraries is that they can exploit the existence of hardware concurrency, in the form of several cores, by carefully using optimized multi-threaded codes.
