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Two-dimensional lattices with the molecular resist architectures are created and combined with the stochastic lithography simulator and a simple etching modeling algorithm, in order to test the transferred line-width roughness (LWR) on the gate region of the pMOS and nMOS transistors of an inverter cell designed with 40 nm nominal gate length.
If the part is mass-produced, an automated transfer line is often the most economical method of production.
The temperature of transfer line was 300°C.
Transfer line temperature was maintained at 260 °C.
A transfer line design problem is considered.
The transfer line temperature was adjusted to 280 °C.
The transfer line temperature was set at 250 °C.
The MS transfer line temperature was set to 250 °C.
This paper presents the design of this transfer line.
This paper deals with a transfer line balancing problem.
This task requires great flexibility in the transfer line optics.
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