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An emerging alternative for computationally demanding digital signal processing is a SIMD-optimized DSP designed for embedded systems, exemplified by the stream processor (or on-chip stream co-processor) [7].
The TDMP algorithm is well suited to implementation on the stream processor if it is used with LDPC codes in which large groups of consecutive row updates can be performed in parallel without data conflicts.
We consider two modifications of the schedule for the TDMP algorithm with early termination; each halves the communication required between functional-unit clusters of the stream processor in each iteration.
Communication among clusters of functional units in the stream processor impose a latency cost during both the message-passing phase and the parity-check phase of the TDMP algorithm with early termination; the inter-cluster communications latency is a significant factor in limiting the throughput of the decoder.
The decoding algorithms reduce by half the data communications required between the stream processor's functional-unit clusters for each iteration of the decoder using the standard schedule.
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The stream processors can be grouped together to perform Single Instruction Multiple Data (SIMD) operations that are suitable for arithmetic intensive applications.
The new flagship card runs at the same core clock speed as the old one, but it has twice the stream processors and texture units and a much-improved memory clock speed.
Then the stream processors of GPU can exchange data with the Global Memory and Shared Memory.
There is also an on-board memory (Global Memory) which can be shared by all the stream processors in a GPGPU.
The basic processing unit in NVIDIA's GPU architecture is called the streaming processor.
The stream-processor architecture is well-suited to decoding a QC-LDPC code using the turbo-decoding message-passing (TDMP) algorithm.
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