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For instruction memory, the IP reassembly benchmark profits heavily from the split memory configuration as it features a highly non-uniform memory access pattern.
The other two constraints allow limiting the available area for the split memory organization and the total number of memory instances.
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Obviously, this interconnect consumes on-chip area and energy itself and may offset the benefits of the split memories.
This allows investigating the effect of split memory configurations of different sizes.
For example, if the most frequently accessed memory addresses are uniformly distributed over the application's address space, frequent and infrequent addresses will inevitably be mapped to the same memory instances voiding any benefit of a split memory architecture.
The resulting optimal power consumptions for each limit are plotted in Fig. 4. For instruction memory, a split memory configuration of only two instances already causes a drastic power reduction (80.5 % for IP reassembly, 67.6 % on average).
With a still very good power reduction of 60.2 %, the MD5 benchmark benefits the least from split memories.
Section 2 discusses existing research in the field of split memories.
Written for three actors, playing characters identified as A, B and C, who represent versions of the same woman at different ages, the play is Albee's most autobiographical, with the split protagonist based on memories of his adoptive mother.
The split component reads k-mers into a memory array until it is full.
You take the split, split, split, split.
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