Sentence examples for the shared bus from inspiring English sources

Due to the shared bus in the Xeon's architecture, delays were greater than the DirectConnect approach of the Opteron, and thus the difference in the stall time.

In this paper, we use simulation platforms developed using the VisualSim tool to compare the performance of two memory architectures, namely, the Direct Connect architecture of the Opteron, and the Shared Bus of the Xeon multicore processors.

In the past, shared bus based architecture was used as a communication architecture in SoC.

Considering that for cost and locality reasons the processing units of these distributed systems are usually interconnected through a shared bus, the underlying communication platform becomes the most important building block.

The second part of the chapter represents a case study that describes the snoopy interregister communication (SIC) protocol that enables communication of the register values and synchronization between the processor cores in the CMP architecture over a shared bus.

The co-processors can be connected either directly to the processors or using a shared bus.

Network-on-chip (NoC) is an emerging interconnect infrastructure to address the scalability limitation of conventional shared bus architecture for many-core system-on-chip (MCSoC).

But the task stealing strategy applied in present run-time systems assumes the sharing the last level cache (LLC) and common shared bus among all cores on Chip Multi Processor.

In this work, we focus on the bus architecture, in which a shared bus is used for communication between processors — and between processors and memories.

Since the proposed tessellator is area-efficient and does not require intermediate memory accesses, its architecture is especially appropriate for the mobile environment, which adopts a shared bus and unified external memory architecture.

While it may have been first to the idea, Shuttl isn't alone in pioneering shared, bus transportation in India.