Sentence examples for the hardware memory from inspiring English sources

Performance is also highly dependent on the nonzero structure of the sparse matrix, the organization of the data and its computation, and the exact parameters of the hardware memory system.

High performance computing on parallel architectures currently uses different approaches depending on the hardware memory model of the architecture, the abstraction level of the programming environment and the nature of the application.

Even though TSLM is quasi-optimal, as mentioned earlier, it is important to take into account the hardware memory and latency induced by this algorithm.

The OpenHMPP directive-based programming model offers a syntax to efficiently offload computations on hardware accelerators and to optimize data movement to/from the hardware memory.

Hardware Transactional Memory (HTM) is an attractive design concept which simplifies parallel programming by shifting the problem of correct synchronization between threads to the underlying hardware memory system.

We have studied the impact of traceback depth parameter ∂, which heavily impacts not only in the PAPR reduction performance but also in the latency and hardware memory requirements.

We have proposed an improvement to the TSLM, which requires very less hardware memory, compared to the originally proposed TSLM, and also have low latency.

Meanwhile, the use of Mapping Bloom filter (MBF) [12] and multi-level hardware memory further improve the lookup speed in MaFIB, reduces the frequency of access to memory and realizes significant reduction in memory consumption.

However, the existing TSLM technique needs very high hardware memory, which also impacts the latency.

We believe that even more performance can be exploited from next generation multicore processors, should they start introducing hardware memory structures like the Message Passing Buffer (MPB) of the SCC NoC processor alongside their cores, for increased communication efficiency among them, without resorting to shared memory and its unavoidable locks or cache-coherency protocol overheads.

This work investigates these ideas by employing application-level task locality for selection of tasks rather than hardware memory topology as is the norm in the literature.