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For HVDC-WASC, initially design the lead-lag blocks for phase compensation at the around of the inter-area oscillation frequency (0.2 Hz ≤ f ≤ 0.8 Hz), and check the compensation performance by means of the root locus analysis.
The guideline for the sequential deign is planned as follows: 1) For HVDC-WASC, initially design the lead-lag blocks for phase compensation at the around of the inter-area oscillation frequency (0.2 Hz ≤ f ≤ 0.8 Hz), and check the compensation performance by means of the root locus analysis.
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