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The test architecture, experiment characteristics and optimal conditions were studied in detail under optimized experiment conditions.
Furthermore, the proposed test architecture can efficiently scale to a many-core with a large number of processing cores.
In this context, asynchronous tests can be more appropriate, reflecting the underlying test architecture which includes queues.
If the distributed test architecture is used then there may be input sequences that cannot be applied in testing without introducing controllability problems.
If these testers cannot directly communicate with one another and there is no global clock then we are testing in the distributed test architecture.
If the testers cannot communicate with one another directly and there is no global clock then we are testing in the distributed test architecture.
Similar(46)
This paper presents a test environment where the designer can quickly evaluate wiring and test time for different test architectures.
In distributed test architectures that utilize remote testers, this objective can be complicated by the fact that testers may encounter problems relating to controllability and observability during the application of a test sequence.
On the other hand, these testing challenges in conjunction with the programmability of FPGAs provide an excellent platform for research and development of new SOC test architectures, strategies, and methodologies, such as silicon debug and diagnosis.
This study addresses the construction of a preset checking sequence that will not pose controllability (synchronization) and observability (undetectable output shift) problems when applied in distributed test architectures that utilize remote testers.
That strategy includes a testing architecture, testing requirements, test cases, and coverage analysis.
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