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Our algorithm avoids dedicated synchronization slots, releasing more time available for data transmission.
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As aforementioned, during the synchronization slot, sources should synchronize frequency and phase in order to make the local signal have the same phase and frequency as that of the received signal.
In synchronization slot, the signal of each source node will be synchronized to the reference signal broadcasted by the destination node; in beamforming time slot, all the transmitting signals of source nodes are coherently combined at the destination node.
Control slots include synchronization slot, broadcast slot, power detection slots, neighboring information upload slots, and schedule assignment slots.
In the synchronization slot, the sources work in receive mode and downconvert the sinusoidal signal broadcast from the destination, sample and convert to digital signal with ADCs, and then send the baseband IQ signal to the synchronization module.
Figure 4 Output waveform of DDS in beamforming time slot is in reverse time sequence to that in synchronization time slot.
To achieve this, the only change of the transceiver is the sign of phase increment, which turns the phase accumulator in the synchronization time slot into a phase decreaser in the beamforming time slot as demonstrated in Figure 4.
Note: that S represents the synchronization time slot during which sources are in receive mode and B represents the beamforming time slot.
The developed MAC protocol minimizes the energy overhead of idle time and collisions by strict frame synchronization and slot reservation.
The reference signal transmitted by the destination node is distributed to two source nodes through Combiner/Splitter 1 in synchronization time slot.
When adopting time division duplex (TDD) mode, our approach can be divided into two time slots: synchronization time slot and beamforming time slot.
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