Sentence examples for static consumption from inspiring English sources

The A/D converter has a resolution of 4 bits for conversion speed of 1 M sample/s with only 264 μW of static consumption in a very particular pitch of 25 μm×900 μm.

For a long time, dynamic power consumption has been considered more significant than static consumption.

A power state is related to an activity of the monitored component or corresponds to a static consumption.

To provide accurate estimation, two kinds of consumption are considered: dynamic consumption related to component activity (e.g., read/write operations), and static consumption related to leakage currents when the component is inactive.

In this setting, I will neglect the standard dead-weight loss considerations since utility losses arising from static consumption and production distortions are typically an order of magnitude too small to be useful in discussions of the Great Divergence (usually 1 2% at most).

where T busy is the time during which the computation is carried out, λ is a hardware constant which represents the ratio of the static power consumption to the dynamic power consumption at the maximum processor speed.

In addition, our proposed design shows almost the same static energy consumption as SLB, and reduces static energy consumption by about 20% compared with the traditional physical cache and virtual cache.

To that end, a nano-electro-mechanical (NEM) relay technology is promising, because of its immeasurably low off-state leakage current and abrupt turn-on behavior, which provide for zero static power consumption and potentially very low dynamic power consumption.

Even our implementation with relatively older generation Xilinx Spartan3 XC3S1500-FPGA0-4 FPGA with its static power consumption of 41 mW provides comparable power consumption performance to that of commonly used processor-based implementations.

The static energy consumption of half of the cells is varied, while the static energy consumption of the other half remains unchanged.

Static power consumption of two cell hybrid CMOS-Nano circuits can be estimated as the sum of static power consumption P ON due to currents I ON,, leakage power consumption P leak due to current leakage through nanodevices in their "OFF" state [24, 25]. Figure 19 shows the equivalent circuit for hybrid CMOS-Nano logic stage.