Sentence examples for speed architecture from inspiring English sources

Most of actual real time simulation platforms have practically about ten microseconds as minimum calculation time step, mainly due to computation limits such as processing speed, architecture adequacy and modeling complexities.

We evaluate our implementation in a testbed of BSD routers over a FastEthernet network, and we sketch how the QoSbox can be implemented in high speed architectures.

This middleware offers better end-to-end bandwidth performance than the traditional TCP-based alternatives, while it hides the heterogeneity of the underlying high-speed architecture.

In this paper, we address this problem and develop a memory-efficient high-speed architecture for multi-level two-dimensional DWT.

We investigate high-speed architectures for the binary tree traversal and show that the traversal approaches discussed can be extended to m-ary tree of height h.

Xiong et al.[13] proposed two line-based high-speed architectures by employing parallel and pipelining techniques, which can perform j-level decomposition for N × N image in approximate 2(1 - 4-j)N2/3 4-j N2/3 4-j)N2/3 4-j N2/3cles.

The company had said little publicly, however, about the speed or architecture of the processor, side-stepping the question of how its performance will differ from the new Celeron.

(Cotter) Morgan Library & Museum Monika Grzymalaa: 'Volumen' (through Nov. 3) A talented Berlin artist, known for conjuring startling intimations of speed or architecture out of little more than masking tape, plays it safe in a work commissioned for the Morgan's airy event space.

(Johnson) Morgan Library & Museum: Monika Grzymala: 'Volumen' (through Nov. 3) A talented Berlin artist, known for conjuring startling intimations of speed or architecture out of little more than masking tape, plays it safe in a work commissioned for the Morgan's airy event space.

In this regard, the semiconductor industry is being severely challenged to produce semiconductor materials of suitable mobility (boosted processing speed) and architecture (for reduced power leakage) on a nanometric scale [1].

This paper presents a novel digital sinusoidal pulse-width modulation (SPWM) technique based on immediate calculation of duty cycle count (DCC) values of pulses with high speed Harvard architecture based RISC controllers.