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Furthermore, the shallower extension of the F4 segment is roughly consistent with another parallel fault line of the Futagawa Fault.
They showed that aftershocks formed a well-defined southeast-dipping plane and that the shallower extension of the fault plane coincided with the active faults on sea floor reported by Katagawa et al. (2005).
In the north of the source region, the shallower extension of the aftershock distribution meets roughly near the surface trace of the Kitakami Lowland fault (cf. Sato et al., 2008).
Due to the shallower extension of this low-velocity anomaly parallel to the dip direction of the oceanic crust, the island arc Moho shows a raised structure near the mantle wedge corner between X = -10 km and X = 10 km.
Figures 3(b) and 4 show that the shallower extension of the planar aftershock distribution seems to meet the surface trace of the RBF estimated by Abe et al. (2008).
We then analyzed the longer-term seismicity from 1990 until the M6.5 Kumamoto earthquake in Region A (see Fig. 4), including the aftershock sequences in Region B of a strong M5.0 earthquake on June 8, 2000, in the shallower extension of the M6.5 Kumamoto earthquake source (Figs. 4, 6a).
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The shallow extension of the aftershock distribution is in approximate agreement with the position of ground deformation (Fig. 4).
Aftershock alignments of these two earthquakes follow on a shallow extension of the westward dipping plane of aftershocks following the 2008 Iwate-Miyagi Earthquake.
We interpret the fault system in the seismic profile as a shallow extension of the seismogenic fault that may have contributed to the resulting huge tsunami.
The sidewall oxide of the insulated shallow extension structure demonstrates the feasibility of the precise control of the halo-to-extension spacing to achieve a sub-50 nm bulk MOSFET with fully CMOS compatible process.
This paper analyzes the effect of temperature variation on various device architectures i.e. Insulated Shallow Extension Silicon On Nothing (ISESON), ISE and SON MOSFET using ATLAS 3D device simulator for 45 nm gate length.
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