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Although the SRAM has half the bandwidth of the SDRAM and a quarter of the DDR SDRAM, it is faster than the SDRAM memories with a block size of 8 byte.
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As shown in Fig. 2, in order for our user-designed hardware module (i.e., both the SRH and DRH) to communicate with the MicroBlaze and the DDR3-SDRAM, it is connected to the AXI4 bus [46] through the AXI Intellectual Property Interface (IPIF) module, using a set of ports called the Intellectual Property Interconnect (IPIC).
It only has 512 MB of SDRAM, but it is upgradeable up to 1.5 GB.
Its appealing size coupled with a fast 2.33GHz Intel Core 2 Duo and an ATI Mobility Radeon X1600 with 256MB SDRAM sets it apart from most competitors.
This implementation is optimized for a 64-bit wide memory bus SDRAM, but it can easily be adapted for other types of memories and supports different image dimensions.
The on-chip memory was chosen because it is the fastest available memory on the FPGA and SDRAM due to its large capacity and its lower cost with a good performance.
Apple doesn't give a figure for its SDRAM memory, but a tear down by ifixit found 256 megabytes of memory.
While memory manufacturers have balked at building the costlier and more complicated Rambus memory chips, Rambus has further antagonized several memory companies by suing them over patents it says it holds on both the older SDRAM and newer DDR.
Here, there are two possibilities: either output the obtained inter-predicted frame or feed it back to the SDRAM memory as the new reference frame.
As a drawback, its required SDRAM controller occupies a major part of the interface.
Therefore, we simulate three different memory technologies: static RAM (SRAM), synchronous DRAM (SDRAM), and double data rate (DDR) SDRAM.
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Justyna Jupowicz-Kozak
CEO of Professional Science Editing for Scientists @ prosciediting.com