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The main overhead of ACQPPS algorithm lies in the block SAD computations.
The SAD computations are conducted with the same area for search ranges with two adjacent backward and forward frames.
Acceleration of 4 × 4 to 64 × 64 SAD computations can be achieved using the aforementioned instructions based on instruction-level parallelism.
As main ME operations are related to SAD calculations that have a critical impact on the performance of hardware-based motion estimator, a fully pipelined SAD calculator is designed to speed up the SAD computations.
With the parallel calculations of basic processing unit (BPU), it can take 4 clock cycles to finish the block SAD computations (BPU for block SAD), and 8 clock cycles to produce a final SAD result for a block.
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The basic operation of the generic subsample algorithm is to find the best motion estimation with less SAD computation.
Two goals are achieved due to the use of online arithmetic (OLA): it is possible to implement a full 16×16 macroblock SAD in a single FPGA device; and it allows us to speed up computation by early termination of the SAD calculation when the candidate involved is bigger than the current reference SAD.
Figure 4 Computation steps of SAD using SIMD instructions.
Obviously, larger block sizes are computationally more costly and the computational burden arising from larger block size in SAD is far greater than the simple gradient orientation map computations in CGO.
Please show all computations.
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