Sentence examples for reduction of clock from inspiring English sources

For further reduction of clock feedthrough and glitch, a deglitcher circuit is used.

The parallel execution leads to a significant reduction of clock and therefore of energy, making embedded high performance particle filters possible, relieving the CPU from a computational expensive task while providing high performance tracking capabilities.

Results of the comparison with another recent genetic algorithm based exploration technique indicated considerable reduction of execution clock cycle as well as power consumption for almost all the benchmarks.

This is achieved by an average 33.4% reduction in the required number of clock cycles below m.

Our hardware evaluation shows a clock speed reduction of 23.2%.

The core idea of the widely used DPM technique, called Dynamic Voltage and Frequency Scaling (DVFS), relies on a combined reduction of the supply voltage and/or clock frequency in a dynamical manner.

Genotypes with a reduction of functional Shaw throughout the clock have lower PDF levels in their LNv terminals, perhaps caused by an accelerated neuropeptide release, which in this case is not correlated with a reduction of behavioral activity.

Furthermore, denervation was accompanied by a loss of circadian release of EPCs and a marked reduction in clock gene expression in the retina and in EPCs themselves.

Given what is known regarding the role of NE proteins in transcriptional regulation, we tested whether reductions in MAN1 expression would affect the transcription of clock genes.

This reduction in amplitude of the oscillation shows that the expression level of Clock mRNA can be affected when C1 increases.

By using the gated clock technique, significant reduction of the total multiplier power consumption is achieved.