Sentence examples for reducing clock from inspiring English sources

The concept of multi-bit flip flop construction has been introduced by recent studies and shown the benefits of reducing clock power and decreasing the total flip flop area in a synchronous design.

In this paper, an efficient algorithm is presented to reduce clock skew variations while minimizing power dissipation and metal area overhead.

Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.

The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary.

Utilizing LC-MBFFs, we propose a multi-bit flip-flop allocation algorithm which fully explores the diverse allocation of LC-MBFF structures to maximally reduce clock power consumption.

In 3 independent time course cultures, treatment with MPA and 8-br-cAMP for 24 hours was sufficient to reduce CLOCK binding to E2 in PER2 promoter by 59%, and this level of repression was maintained over an 8 day time course (Fig. 3 C ).

4) Reducing the clock frequency.  .

Tool-path neighbours are grouped and simulated in parallel, greatly reducing wall clock running time.

This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect.

The proposed hardware additions provide 30% speed improvement over software solution, thereby reducing the clock rate required to process full-rate video from 300 MHz down to 213 MHz.

To reduce the clock jitter, one clock is used to generate the clock sampling signal.