In [7], the authors present a comprehensive survey of state-of-art techniques aiming to address the challenges to ICN caching technologies, with particular focus on reducing cache redundancy and improving the availability of cached content, and also points out several interesting yet challenging research directions in the caching study area.
This paper presents a comprehensive survey of state-of-art techniques aiming to address these issues, with particular focus on reducing cache redundancy and improving the availability of cached content.
Hash routing reduces cache misses for a cluster of web proxies by eliminating the duplication of cache contents.
First, to reduce cache misses, we propose an on-chip cache compression method that drastically increases compression performance over prior work.
Content-based routing reduces cache node CPU cycles but can make the front-end router a bottleneck.
The evaluation model is constructed, and the result demonstrates that the proposed method can reduce cache miss penalty dramatically.
There have been numerous techniques proposed in the literature that aim to improve the performance of cache memories by reducing cache conflicts.
In addition, this technique decreases the average delay per task and total power consumption by reducing cache misses and avoiding unnecessary data transfers.
Moreover, SPARC16 reduces cache miss rates up to 9%, requiring smaller caches than SPARC processors to achieve the same performance; a cache size reduction that can reach a factor of 16.
To attain such performance on real shared-memory machines, our algorithm computes convolutions converging on the same node of the network with temporal locality to reduce cache misses, and sums the convergent convolution outputs via an almost wait-free concurrent method to reduce time spent in critical sections.
We extend study of the performance of the flux kernel to the Xeon Phi in three thread affinity modes, namely scatter, compact, and balanced, in both offload and native mode, with and without various code optimizations to improve alignment and reduce cache coherency penalties.
