Another type of disturb, read disturb, occurs when a cell is read many times.
Typically, there are two main types of failures that occur during the read operation: read disturb and false read.
This paper shows the operation and reliability aspects of 2T N-type SONOS memories: endurance, retention and read disturb.
The compensation implant is shown to work in long channel cells to optimize bit coupling, read disturb, and program speed.
An experiment of read disturb is performed on HfO2 based MIM devices designed for resistive memories (RRAM).
However, the direct tunneling cannot be turned off at a low electric field, leading to poor retention and read disturb.
However, co-doping with compensation implant fails at short channel length to reduce read disturb thus bit coupling at safe read VD.
In this case, read disturb is completely avoided and the advantages of the 2T NOR architecture are fully used, meaning fast random access and real low power operation.
The analysis and simulation results demonstrate that the proposed cell eliminates read disturb issue and outperforms the state-of-the-art 9T TFET bit cell in terms of static and dynamic write performance.
The junction engineering scheme is shown as the possible alternative for successful scaling of cells to simultaneously reduce read disturb and bit coupling but at the expense of program speed, which seems detrimental for deep scaling of cells.
