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To comply with ITER-relevant constraints an adapted radiation qualification procedure has been proposed.
The qualification procedure and the results obtained in the laboratory are presented.
Moreover, the possible failure modes were identified in order that a design and qualification procedure was recommended for engineering application.
The analyzed NEA/OECD core transient benchmarks have been recently added to the developed TRAC-PF1/NEM qualification procedure.
The Bosch space experiment clearly demonstrates these benefits, and it also shows the applicability of the technology with respect to space qualification procedure.
This paper describes the radiation qualification procedure for a 1 MGy-tolerant Application Specific Integrated Circuit ASICC) developed in 65 nm CMOS technology.
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At the same time, American visa qualification procedures became intensely restrictive and suspicious.
The radiation-qualification procedure describes the test criteria and test conditions of the developed ASICs, which are also compared with COTS alternatives, to meet the stringent qualification procedures for electronics exposed to radiation in ITER.
The results were presented of unadjusted and adjusted stylus/probing system qualification procedures.
To have a uniform performance of all modules standard qualification procedures have been developed.
The performance criteria for the HPDs is outlined, along with the qualification procedures carried out at dedicated test facilities.
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