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Hence, the embedded SMQ proposes a memory requirement that is much lower than that of a nonSMQ of the same resolution.
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We propose a memory and communication centric design methodology to reach an energy-efficient dedicated implementation.
In this paper, we propose a memory state feedback model predictive control (MPC) law for a discrete-time uncertain state delayed system with input constraints.
In Section 3, we propose a memory-3 MNBTC with two inputs offering a good trade-off between performance and complexity.
We have adapted the behaviour subtraction training process to take advantage of the expected horizontal invariance of background behaviour, and propose a memory-saving implementation.
In this paper, we propose a memory-based global differential evolution (MGDE) algorithm and a repair technique of constraint handling for the dynamic economic dispatch problems.
Hsia et al.[6] have proposed a memory-efficient dual-scan 2-D lifting DWT architecture with temporal buffer 4N and critical path of two multipliers and four adders.
In this paper, we analyze the characteristics of the Snort rule set, and propose an memory-efficient multimatch packet classification architecture for NIDS using the result of analysis.
This research study proposes a new memory-type control chart.
The paper proposes a shared-memory fault tolerant multiprocessor architecture for Computer Aided Manufacturing management and control, where an Ethernet LAN is used to connect FMC associated Station Computers to the shared memory residing in a supervising CAM server.
This paper proposes an efficient memory controller for video and image processing to reduce the latencies for reading and writing blocks of pixel data.
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