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Since the intended deployment platform is an FPGA, HW/SW partitioning issues are also considered as well as code profiling accomplished to validate the proposal, showing some preliminary results of the proposed hardware architecture.
This proposed hardware implements Tempest using a fully-programmable, user-level processor in the network interface.
Some experiments with that emphasize advantages of the proposed hardware implementation.
The application of the proposed hardware is shown in image compression.
The proposed hardware architecture replaces the necessary multiplication by shift-left operations.
The proposed hardware and software were created within Project-Based Learning classes.
The proposed hardware architecture and sensors form a low-cost and reliable control unit.
This reconfigurability characteristic permits that any application of ANNs may be implemented using the proposed hardware.
The proposed hardware and software have been tested by detecting a resin rich region formed between the E-glass/epoxy plies.
Also, the performance of the proposed hardware is compared against a soft core embedded processor named NIOS II/s.
High performances are reached by the proposed hardware implementation, moreover, flexibility is guaranteed by the configurable architecture.
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