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The authors propose a processor architecture that meets these design principles.
In this paper, we propose a processor allocation technique for such an efficient and fast PA.
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In [19], the authors propose a reconfigurable multi-processor approach in order to decode multiple data streams in parallel.
Serres et al. [15] presented a reconfigurable multicore scenario based on LEON3 soft-processor and proposed a co-processor interface for each core.
This paper, instead, proposes a reactive processor for the direct execution of Esterel.
This paper proposes a new processor architecture called VVSHP for accelerating data-parallel applications, which are growing in importance and demanding increased performance from hardware.
Finally, we propose a new stereo matching processor.
Zhong et al. [20] proposed an DFT/IDFT processor based on multi-processor rings.
We propose a multiprocessor model with one processor per thread.
We propose a fully pipelined, multithreaded, reactive processor called STARPro for direct execution of Esterel.
More specifically, we propose a Lightweight Stage-based Event Processor (LiSEP) based on a layered architectural design.
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