Exact(6)
In this paper, we propose a hardware (H/W) architecture to find disparities for stereo matching in real time.
To address this issue, we propose a hardware accelerator for solving sets of linear equations based on iterative methods.
With regard to these issues, in this paper, we then propose a hardware based approach, named "Forwarding Unit" to provide an effective solution to these drawbacks and improve the efficiency of server-centric architectures.
In this paper, we derive an HEC hunting algorithm for bit-level and octet-level operations and propose a hardware circuit to simplify the implementation of an SDL framer.
The aim of this paper is to propose a hardware and software framework that is self-contained with on-board sensing and computation and that can be applied to vehicles and robots of different nature and having in common the characteristics of being underactuated, intrinsically unstable and with a limited number of actuators.
Suppose the LDPC code with code length N and expansion factor z f still has serious memory conflicts though being optimized by our SA and ACO algorithms, which is common for large z f and relatively small N. To address this problem, we propose a hardware method called "multi-block" to further avoid memory conflicts and increase pipeline efficiency.
Similar(54)
In this paper, we proposed a hardware implementation method for generating a sandwich hyperchaotic attractor.
NXP proposes a hardware architecture featuring a VLIW vector processor named EVP [20] targeted to support 3G standards.
A bit of background, in the 90's, the government proposed a hardware backdoor to cell phones, known as the "Clipper Chip".
This work proposes a hardware architecture to implement an artificial neural network (ANN), whose topology is the multilayer perceptron (MLP).
In [39], we proposed a hardware architecture for specific OFDM waveforms (i.e., WiFi and DVB-T) based on the cyclostationarity algorithm presented in [28].
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