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Processor array architectures are optimal platforms for computationally intensive applications.
Further, the preprocessing phase is also accommodated onto the same processor array designs.
In this paper, we present linear processor array architectures for flexible approximate string matching.
We are proposing a Customizable Embedded Processor Array for Multimedia Applications (CPAMA).
In the PADMAVATI prototype system, a hierarchy of packaging technologies cascade multiple SPACE chips to form a 170496 processor array.
The result shows that the video processor array structure achieves a maximum operation frequency of 165.2 MHz.
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less than two percent area overhead per PE, for a class of reconfigurable processor arrays called Tightly Coupled Processor Arrays (TCPAs).
We study the degradable processor arrays to achieve fault tolerance by employing reconfiguration.
Three bypass schemes and three rerouting schemes are proposed to reconfigure three-dimensional processor arrays with defective processors to achieve target arrays without faults.
Homogeneous processor arrays are emerging in tera-scale computation and effective fault tolerance techniques are essential to improving the reliability of such complex integrated circuits.
The computing power of MPSoCs can be further augmented by adding massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions.
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