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To correct for this, we introduce an additional processing block (process 4).
In order to complement this first-order correction and to allow the DLFI chain to also operate independently of the SCARF sequences of model production, an alternative processing block (process 3) is used.
The upper way, Figure 2, is the processed data flow which passes through the process block (data processing block) and then feeds the convolution encoder (parity regeneration) to produce parity values.
In our implementation, a processing block is realized as an individual process expecting well-defined input data and generating output consumable by subsequent blocks.
Table 8 Processing block power consumption estimation.
Fig. 1 Processing block diagram of the proposed algorithm.
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Using separate processes instead of threads for the processing blocks offers a number of benefits.
The received preamble is processed right after the IFFT in the receiver, i.e., the subchannel processing blocks in Figure 1.
Using energy-efficient processing blocks.
The blocks constituting such receiver are referred to as soft-input soft-output (SISO) processing blocks.
Designers can write their own signal processing blocks if needed and integrate them in GRC.
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