Stego key is generated from a password (pwd) by sender and receiver using pseudo random number generator (PRNG) [1].
The known sensitiveness of GAs to the choice of the PRNG motivated the option to a high-quality PRNG [36].
In this work we will use the Mersenne Twister PRNG [53], which has a period of (2^{19937}-1).
The resulting Split-LUT-Carry SPCA (SLC-SPCA) PRNG achieves 6x improvement in logic density compared to LUT-SR, and a 1.5x density increase compared to SPCA.
The MWC PRNG uses only 3 registers per thread and features a period of ~2.
In this paper we explore the SPCA structure and derive a set of parameter constraints which allow a SPCA PRNG to produce 2 random bits per LUT in every clock cycle on modern Xilinx FPGAs.
In order to start the hash-chain, an initialization phase is required: A trusted third party (mathcal {T}) selects a random number s as seed for the PRNG and thus generates (r_0) by using the PRNG on s.
If (13) is not satisfied, the inferior limit expressed by (11) is assumed to be 0. is derived by a PRNG (pseudo random noise generator) seeded by the stegokey according to (11) and (12). .
Due to the slow and statistically bad PRNG used in the original MCML implementation [ 11, 24], the PRNG was exchanged for the well-known double precision, SIMD-oriented Mersenne Twister random number generator [ 25, 26].
The Mersenne-twister, the 24 and 48 bit RANLUX and a 'minimal-standard' PRNG are supported.
Therefore, the PRNG solution used by Alerstam et al. in [ 14] and [ 19] the Multiply-With-Carry (MWC) algorithm by Marsaglia [ 23] is instead used in GPU-MCML.
