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In this paper, we present a clock routing algorithm, called PMXF, to construct an X-architecture zero-skew clock tree with minimum delay.
They present a clock sampling algorithm which tolerates attacks by this adversary, collisions, a bounded amount of losses due to ambient noise, and a bounded number of captured nodes that can jam, intercept, and send fake messages.
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This paper presents a clock and data recovery (CDR) topology that can adjust the power consumption with its input bit-rate.
It also presents a pausible clock generator application and simulation results for the proposed architecture.
Circadian clocks present a particularly interesting instance of this.
In this paper, we present a simulation study on clocking misalignment tolerance of pipelined magnetic quantum-dot cellular automata (MQCA) architectures.
In this paper, we present a method for distributing clocks and triggers between 4 PXI chassis containing DGF Pixie-16 modules with up to 226 acquisition channels per chassis.
Here we present a comparative overview of clock-associated components and the circadian network in the moss P. patens.
We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems.
Now Tokyo-based toy and video game maker Banpresto presents an alarm clock in the shape of a Japanese railroad crossing sign.
Given our criticism of some of the calibration points used in molecular clock studies, we present a more conservative, and better justified, set of points (Table 3).
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