Sentence examples for pipeline level from inspiring English sources

Five are considered herein and include inventory recovery to "shock" demands; in-built filtering capability; robustness to production lead-time variations; robustness to pipeline level information fidelity; and systems selectivity.

o Maximum soil displacements at the ground and pipeline level were predicted to be about 80 mm, and 10 mm, respectively.

The pipeline level and the schedules of neural controller computation process flow are given in Figure 5, and the pipeline stages are marked by lowercase letters (a, b, c,…, g) in Figure 4.

As shown in Fig. 6, only the raw JSON data will go through this transformation, as the pre-transformed Avro file has already been transformed at the data pipeline level and the raw Avro data will be transformed at the analytic time when it is required.

For the case study dealing with a pipe buried at a depth of 2.7 m (a relative depth ratio (DR) of 0.9 within the active soil zone): o Maximum soil displacements at the ground and pipeline level were predicted to be about 80 mm, and 10 mm, respectively.

The proposed pipelined divider could achieve the same throughput rate as the existing ones by using nearly half the number of pipelining levels.

Not limited to this pipeline-level abstract view, users can click through to see details on each component and down to the level of each individual command, allowing any individual command line string to be copied and run within a terminal.

Such innovative financial instruments allow the development of a spot market for natural gas, which ensured that gas price reflect underlying issues of demand and supply, such as the availability of power plants, hydro levels, gas storage levels, oil prices, pipelines, temperature, level of industrial or commercial demand); and not just "track" that of oil prices, as was the case before.

There is no Keystone pipeline, drilling levels are virtually the same as when prices were increasing, and EPA regulations are still in place.

We used a combination of both approaches by building a pipeline of level-set algorithms, starting with the one most robust to poor initialization and finishing with the most accurate.

The chip comprises fast front-end and amplitude discriminator circuits using bipolar devices, a binary pipeline for first level trigger latency, a second level derandomising buffer and data compression circuitry based on CMOS devices.