Sentence examples for pipeline hardware from inspiring English sources

An intuitive method is also used to describe timing views for functions mapped to pipeline hardware.

In this paper, a high throughput and high accuracy full-pipeline hardware architecture with disparity and row parallelism is proposed.

Combined with a new pipelined hardware implementation, the new design achieves better performance.

Two of the well-known algorithms namely Montgomery modular multiplication and Karatsuba algorithms are exploited together within our high-speed pipelined hardware architecture.

However, pipelined hardware implementation of these algorithms has two major issues: (1) backtracking which causes stalling the pipeline and (2) memory inefficiency owing to variation in the size of trie nodes.

A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations.

A pipeline architecture is implemented on about 100 pipelined hardware processors to perform this job.

The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation.

The proposed approach, thus, has a considerable advantage over aerial solutions since it is able to achieve higher fall classification performance using a simpler algorithmic pipeline and hardware setup.

Comparisons of computational speed with respect to the literature is somehow difficult to infer since (1) not every work declare computational speed, (2) only isolated blocks of the alignment chain are usually considered (e.g. feature extraction) instead of the entire pipeline, (3) hardware obsolescence.

Further, pipelining reduces hardware resources.