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A pipeline architecture is implemented on about 100 pipelined hardware processors to perform this job.
HORN computers have a pipeline architecture.
The special purpose computer is constructed using pipeline architecture.
The pipeline architecture of the multiplier component increases the clock frequency and the throughput.
The algorithm is executed on the DM-MIMD Alex AVX-2 machine using a pipeline architecture.
When implemented in hardware pipeline architecture, our mechanism can achieve one routing lookup per memory access.
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In this paper, efficient pipeline architectures that implement the 2-D FFT are presented.
Three different pipeline architectures for realtime implementation on a FPGA-based smart camera are then discussed.
The pipeline expression language sits on top of SystemC, exposes all of the features of C++ and SystemC enabling the user to specify, evaluate, and analyze pipeline architectures.
First, it is evaluated the influence of control flow and pipeline architectures combined with the use of specialized DSP blocks in the FPGA.
In this paper, regular fast algorithms for discrete cosine transform (DCT) and discrete sine transform (DST) of types II IV are proposed and mapped onto pipeline architectures.
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