Complexity analysis and extensive simulation results are presented and illustrate that MLDDRR is a high-performance packet scheduler and suitable for being deployed in future high-speed networks to provide relative delay differentiated service.
SRIO is a high-performance, packet-switched, interconnect technology.
It is a high-performance, packet-switched protocol that was developed to address the embedded industry's need for faster bus speeds, increased bandwidth, reliability, cost effectiveness, and scalability.
Several metrics are used to measure the transmission performance, including packet loss rate, packet jitter, throughput, path cost, and average link utilization.
Our fully hardware based event-driven architecture has comparable cycle count performance in packet transmission and 30% less cycle count for packet reception as compared to the event processor-based architecture (implemented on general purpose processor).
We can finds when their performance for packet delivery ratio is very close, their performance for packet average delay is very close.
The increase of performance of packet delivery ratio is exchanged by the decrease of performance for packet average delay.
We consider the following performance metrics: Packet delivery ratio (PDR): Ratio of the number of data packets received at the destinations to the number of data packets generated by the CBR sources.
From our network simulation results, we conclude that predictive circuit switching exceeds the performance of packet switching for highly predictable traffic, like collective communications, and for heavily loaded unpredictable traffic with small packet sizes.
LBAR shows better performance in packet delivery ratio and routing overhead, but there is no big difference in residual energy ratio, and packet average delay becomes even worse in some case.
Moreover, DTBR will bring a profit for the performance of packet delay and network throughput compared with other routing algorithms.
