Sentence examples for partial parallel from inspiring English sources

In this paper, three different implementations of a multistage partial parallel interference cancellation (PIC) receiver for the asynchronous UMTS signal are presented and compared.

The textures of the cold rolled specimen were characterized according to the 〈110〉 partial parallel to the rolling direction as the rolling reduction increased.

A 2D EPI sequence with partial parallel imaging acceleration was utilized to gain 3 × 3 mm in-plane resolution in 3-mm axial slices with a 1-mm slice gap.

Some group divisible design (GDDs) with orthogonal resolutions, one is a set of parallel classes and the other is a set of partial parallel classes are constructed from Baer subplanes.

Three k-space acquisition techniques were compared for image quality and SNR: (1) generalised autocalibrating partial parallel acquisition (GRAPPA) with an internal acquisition of reference lines, (2) GRAPPA with a single "external" acquisition of reference lines before the measurement, and (3) a combination of GRAPPA with an internal acquisition of reference lines and view sharing.

Procedure of partial cancellation factor (PCF) selection for the first stage of hard-decision partial parallel interference cancellation (PPIC) using GR employed by direct-sequence code-division multiple access (DS-CDMA) systems under multipath fading channel in the case of periodic code scenario is proposed.

Partial-parallel architectures for high-throughput LDPC decoding have been proposed by Mansour et al. [11, 12], where the concept of architecture-aware LDPC codes was firstly introduced.

The design of partial-parallel solutions generates systems with lower areas, but also implies lower throughputs, comparing to full-parallel architectures in a SoC.

A partial-parallel pipelined VLSI architecture is developed to implement the algorithm with high throughput, low processing latency, while offering the flexibility to support run-time performance tuning.

An efficient partial-parallel block-layered decoder architecture suitable for the proposed forward-backward four-way merger algorithm is presented to speed up the decoder convergence.

Compared with full-parallel decoders, the complexity of an interconnection network in a partial-parallel architecture significantly decreases, which eliminates important restrictions from the routing process (in the place & route phase of the design).