Classic enhancements in computer architectures are pipelining, instruction and data caching, dynamic branch prediction, out-of-order execution, speculative execution, and fine-grained chip multithreading.
Processors have evolved into two main categories, namely, in-order execution and out-of-order execution.
One of the critical changes is the employment of in-order execution instead of out-of-order execution.
In a processor that supports out-of-order execution, the execute stage can process instructions in a different order than was specified by the executable and can dynamically reorder instruction execution based upon resolution of dependencies.
Dynamically scheduled, superscalar microprocessors combine several parallel execution units with an out-of-order execution to extract the ILP from the instruction stream.
It allows sequential instructions that would normally be stalled due to certain dependencies to execute non-sequentially (out-of-order execution).
All these features, such as multilevel caches, branch target buffer, out-of-order execution, and speculation, include a state that heavily depends on a large execution history.
In-order and out-of-order execution describes how instructions are processed by the execute stage of the processor pipeline.
More precisely, it executes the instructions serially as in-order execution until a stall condition is encountered, and thereafter, it uses of concept of out-of-order execution to replace the stall with an independent instruction.
The issue queue in an out-of-order execution processor is a major power consumer.
me: "I'm awash with danger". R. M. Tomasulo was a pioneer in out-of-order execution.
