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A frequency encoded all optical N bit comparator is proposed.
An N bit number can represent one of 2N possible values.
The latency of the architecture is n/2 clock cycles and throughput rate is one valid result per n/2 clocks for n bit precision.
Figure 3 Signed 8-bit multiplication using modified booth algorithm- N bit multiplication.
During N bit multiplication, negk bits are added in the LSB part of each partial product row.
The signal selection x/y in Table 1 represents partial product (P) for N bit/ P for N/2 bit multiplication.
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A scalable cell consists of n bit-level cells and has both hardware and bijective scalability.
While the longest carry propagation of an n-bit adder is n bits, its expected length is only O log2 n) bits.
Let c1,..., c l be the l clusters after clustering the set of N bit-patterns.
Any adder can be used to perform the n-bit addition of the DCAS cells.
This paper describes the design of n-bit adders using these MTTGs.
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