Sentence examples for multiple adder graph from inspiring English sources

When compared with the recently proposed multiple adder graph (MAG) algorithm [Jeong-Ho Han, In-Cheol Park, FIR filter synthesis considering multiple adder graphs for a coefficient, IEEE Trans. Comput.-Aid. Design Integ. Circuit Syst. 27 5) (2008) 958 962 (May)], the average reduction of logic operators obtained using our method is 5% and the reduction of logic depth is 25%.

We also show that the HWP can also be employed to overcome the limit imposed on the word length of the coefficients for the reduced adder graph (RAG) algorithm and filter coefficient synthesis.

These operations form a so-called adder graph, so this method is called the adder graph MCM method in the following.

A reduction of pipelined operations by 10% compared to the optimal pipelined adder graphs [8] could be achieved by the reduced pipelined adder graph (RPAG) algorithm [9].

The SOP circuit of Figure 2a can be either obtained by using LUT multipliers and additional adders, or by transposing the adder graph which was obtained by an adder graph MCM method.

It is well known that the adder cost for a single-input single-output adder graph is equal to its transposed form [44].

One objective is minimizing the power of the adder graph by reducing or minimizing the adder depth (AD) of each output, which is defined as the number of adder stages needed to compute a coefficient [26 29].

Instead of placing pipeline registers after each stage of adders, they could be placed behind multiple adder stages (e.g., every second or third stage).

For B x  = 8, all instances were pure LUT MCM realizations; for B x  = 10, there is a mixture of pure adder graphs, pure LUT realizations, and combinations of both; while for B x  = 12, the adder graph realizations dominate.

The results are summarized in Table 2 for RPAG (R = 1 and R = 50) and the LUT MCM method which are compared to the proposed pipelined adder graph (Optimal PAG) and pipelined adder/LUT graph (Optimal PALG) methods.

Fig. 13 a Two-input adder graph by PAG algorithm for the multiplier block {87,381; 689,493} and b three-input adder graph by PAG algorithm for the multiplier block {87,381; 689,493}.