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The main modules of the receiver are a properly designed ΔΣ-modulator for A/D-conversion, and novel digital filtering stages.
The main modules of the receiver are the discrete wavelet transform unit and ANN, as illustrated in Fig. 1 b.
The complexity has been evaluated for a Xilinx Kintex-7 FPGA and is given by the amount of slice registers, look-up tables (LUT) and DSP48E1 cells used by the different modules of the receiver design.
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Figure 12d shows the distance between the transmitted data frames, and Figure 12e presents an example of the received data frame at the output of the XBee module of the receiver with the corresponding clock signal clk_lz.
The first module on the receiver side is the Hilbert transformer.
The above steps form the module I of the receiver section.
The modules of the transmitter and receiver are implemented, and numerical simulations demonstrate the effectiveness of the system.
The reception module (in Figure 2) of the receiver is dedicated to receiving signals on the corresponding residue subchannel.
FFT and Memory Unit are common modules, while the remaining of the receiver should be duplicated as many times as the number of parallel asynchronous users the system may tolerate.
Figure 7 The block diagrams of the receiver modules: (a) audio and (b) video.
The first three modules constitute the transmitter side and the other modules the receiver side.
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