In the delay-constrained transmission mode, the throughput efficient in the time slot ith, which is the function of outage probability and the EH duration time, can be formulated by tau_{i}^{DC} = left({1 - O{P_{i}}} right)left({1 - {alpha_{i}}} right).
Thus, from a managerial point of view, the core issues of the cure mode are throughput time and the amount of patient-in-process inventory, supported by sequencing, process flow, and handovers.
Additionally, a GPU verification platform is built that can accelerate 490× speed against CPU and a multi-mode high-throughput decoder is implemented on FPGA, achieving a net-throughput 1.2 Gbps and performance loss within 0.2 dB.
The top level architecture is shown in Figure 6. Figure 6 Top-level multi-mode high-throughput LDPC decoder architecture.
Our goal is to implement a multi-mode high-throughput QC-LDPC decoder, which can support multiple code rates and expansion factors on-the-fly.
One great advantage of the proposed multi-mode high-throughput LDPC decoder is that more modes can be supported with only more memory bits consumed and no architecture level change.
Based on the above techniques, namely, reconfigurable switch network, offset-threshold decoding, split-row MMSA core, early-stoping scheme and multi-block scheme, we implement the multi-mode high-throughput LDPC decoder on Altera Stratix III FPGA.
Compared to existed FPGA or ASIC implementations [14 16], the proposed multi-mode high-throughput decoder not only supports multiple modes with completely on-the-fly configurations, but also has a performance loss within 0.2 dB against float precision and 20 iterations, and a stable net-throughput 721.58 Mbps under code rate 1/2 and 20 iterations.
Finally, detailed implementation schemes are proposed, i.e., reconfigurable switch network (adopted by [13]), offset-threshold decoding, split-row MMSA core, early-stoping scheme and multi-block scheme, and the corresponding multi-mode high-throughput decoder of the optimized codes is implemented on FPGA.
