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Hardware designs need to obey constraints of resource utilization, minimum clock frequency, power consumption, computation precision and data range, which are all affected by the data type representation.
Such constraints have brought forth what we know as "dark silicon", the area of a chip which should be turned off or work on a minimum clock frequency to meet the power dissipation constraints.
Figure 7 Minimum clock frequency requirement to achieve maximum system throughput.
Execution cycle count and minimum clock frequency requirement are measured using ModelSim simulator.
For performance analysis, the execution cycle count and the minimum clock frequency requirement to achieve the maximum possible throughput are recorded.
Figure7 shows the minimum clock frequency requirement of our FPGA based implementation to maintain 250 kbit/s system throughput (the maximum possible data rate through CC2420 based wireless interface) for typical sensor node tasks described earlier in this section.
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This frequency has been chosen in regard to RDecASIP maximum clock frequency [31].
The optimum point for reliable start of the charge pump has been observed for the clock frequency of about 160 kHz, where the minimum start-up voltage of 126 mV is needed.
For example, the time taken by PIC16LF88 to complete an analog to digital conversion is 65.974 µ s, including 54 µ s computation time (108 instructions with 8 MHz clock frequency) and 11.974 µ s acquisition time (minimum required acquisition time [27]).
The frequency scaling scheme of this paper selects the minimum clock speed that satisfies the requirement of the CMMB standard based on the estimated SNR.
On the other hand, in the proposed design, the clock frequency of 85 MHz satisfies the throughput requirement for CMMB when the SNR is 2.5 dB. Figure 6 Minimum operating frequency vs. SNR.
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