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For example, many previous studies focusing on minimizing the memory usage have developed on-disk indexing schemes, leading to lower performance.
In this context, GPGPU data caches and shared memory have a key role since they allow to increase performance by sharing data between the parallel resources of a GPGPU and minimizing the memory accesses overhead.
While minimizing the memory requirements of operating systems for standard computers has been important, it has been absolutely essential for small, inexpensive, specialized devices such as personal digital assistants (PDAs), "smart" cellular telephones, portable devices for listening to compressed music files, and Internet kiosks.
The main contribution of this work includes a novel technique for minimizing the memory bandwidth bottleneck, a new priority scheme and a new set of heuristics which target on the maximization of the Instruction Level Parallelism by efficiently managing the architecture's resources.
For instance, minimizing the memory distance between two functions that frequently communicate reduces the energy consumption of target application [32].
To solve this problem, research [12] has often proposed a data reuse alternative with the aim of minimizing the memory traffic between GPU and CPU.
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To show feasibility of the approach, we formulate an ILP problem to minimize the memory access times.
We also propose a rule categorization algorithm that partitions an input ruleset by considering the field features of rules to minimize the memory requirement.
Exploiting bitmaps not only minimizes the memory consumption, but also reduces CPU costs.
Matching information of already computed patterns is materialized as bitmaps, a technique that not only minimizes the memory consumption, but also the CPU time.
Following an 'S'-shaped path minimized the memory demands inherent in the task relative to if a more irregular path was followed (Gilchrist et al., 2001).
More suggestions(15)
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