Sentence examples for memory window shows from inspiring English sources

The memory window shows no degradation after 106 ac switching cycles, as shown in Figure 4.

However, the current in HRS increases after about 100 dc voltage sweeping cycles, which leads to the memory window closing, as shown in Figure 4.

As compared to the device with HfON/SiO2 dual tunnel layer (DTL), the one with TaON/SiO2 DTL shows larger memory window (3.85 V at ± 13 V/1 s), higher program/erase speeds (1.85 V/−2.00 V at ± 12 V/100 μs), better endurance (window narrowing rate of 5.7% after 105 cycles).

Meanwhile, it also shows a large memory window.

Figure 8 shows that a 1-V memory window can be obtained at P/E times of 10/10 ms, which shows a sufficient memory window even at a ±2-V applied pulse voltage.

The results showed that the memory window was increased from 11 to 14.6 V, corresponding to increasing the number of charge trapping layers from two to three.

The band-engineered charge trap (CTD) device with (HfO2)x(SiO2 1−x/SiO2 double dielectric structure showed faster program/erase speed and larger memory window at same time and voltage compared to the CTD with a single SiO2 tunnel barrier.

Inset shows the dependence of the width of memory window on Vgmax.

Obviously, the width of the memory window increases with Vgmax, and the device's on/off ratio shows negligible change when Vgmax is larger than 6 V.

The memory device exhibits a large memory window of ~2.6 V under ±8 V sweeping voltage, and it shows only ~14% charge loss after more than 10 years' retention, indicating excellent charge retention properties.

A 1-V memory window was observed for A4 at the ±2-V sweep (Figure 8), which shows the potential to prepare a low-voltage NC memory.