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For the sample with 1.5 nm-HfAlO/3.5 nm-SiO2 tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO2 tunnel layer.
The memory window is found to higher at low frequencies.
Furthermore, the memory window is found to be the function of frequency and higher memory window is achieved at the lower frequency region.
The memory window is opened to 5.2 V for 1 s.
The memory window is high only at lower frequencies (1 and 2 Hz) and tends to diminish at higher frequencies.
At room temperature, no obvious degradation of the memory window is observed with slightly increasing LRS and HRS.
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An extra-large memory window was also obtained by introducing photo-induced charge transfer effect.
A faster program/erase speed as well as a larger memory window was achieved from the TBE-CTF memory.
Using the model, the thickness effects of the ferroelectric and insulator layers on the capacitance voltage (C V) characteristic and the memory window were investigated for Pt/SBT/ZrO2/Si and Pt/BLT/MgO/Si structures.
While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm.
The obvious memory window was found in the capacitance voltage hysteresis curve, and the program efficiency of holes was superior to electrons due to the electronic affinity of GeO2 smaller than silicon substrate for a structure of Ge nanocrystals surrounded with GeO2 layer.
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