Since the formation and application of concepts requires memory, sense-perception, so conceived of, does not involve conceptualization, either.
In particular, since NAND flash memory on-chip sensing latency is linearly proportional to the sensing quantization granularity, soft-decision memory sensing will largely increase on-chip memory sensing latency compared with current practice.
The major conclusion is that the functional diversity of frugivores (memory, senses, mouths, guts etc).
This clearly shows the linear dependency of memory sensing latency on the number of sensing quantization levels.
Meanwhile, in the presence of soft-decision memory sensing, the flash-to-controller data transfer latency will accordingly increase.
Meanwhile, the error correction capability of LDPC code decoding gradually improves as we increase the memory sensing precision.
The linear dependency of memory sensing latency on the number of sensing quantization levels is caused by the underlying NAND flash memory structure.
Today's modern mobile devices are equipped with more powerful processors, operating systems and have a range of computational, memory, sensing, communication, and storage resources.
Figure 1 Illustration of NAND flash memory sensing, (a) Illustration of NAND flash memory structure, and (b) illustration of word-line voltage sweeping for memory sensing, all the bit-lines are charged and discharged once for each word-line voltage point.
To meet a specified P/E cycling endurance limit, the LDPC code decoding with the maximum allowable soft-decision memory sensing precision should be able to tolerate the worst-case raw storage reliability at the end of memory lifetime.
This can directly reduce the average latency of on-chip memory sensing and flash-to-controller data transfer caused by the use of LDPC codes in NAND flash memory.
