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A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs.
However, when the ratio of arithmetic operations to memory operations is high, the GPU may "hide" the memory latency by using the waiting time to do calculations with other threads.
The maximum number of atomic memory operations is reduced to the total number of photon packets launched (since reflectance/transmittance is recorded atomically only upon exiting the tissue, which happens once per photon packet) and these operations are spread out over the entire simulation.
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All data processing instructions take place between registers and all memory operations are restricted to memory-to-register load operations and register-to-memory store operations.
The internal memory operations are handled in a separate scenario.
As mentioned in Section 5.3 the internal memory operations are separately handled.
Two categories of memory operations are included in the instruction set of the C6416T DSP load and store.
This, along with the gain in speed provided by in-memory operations, is the real reason, in my opinion, for its growth in popularity.
In-memory operations are, on average, 30 times as fast as operations requiring disk I/O.
This parallel, shared-memory operation is extremely efficient, both for speed and power usage, but it puts a heavy demand on the computer's ability to interleave and properly order memory usage.
In addition, this result illustrates the strength of GPU-based calculations; GPUs are good at handling organized (coalesced) memory operations (which is hard to achieve in MC applications), but perform poorly with random memory operations and atomic memory operations.
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Justyna Jupowicz-Kozak
CEO of Professional Science Editing for Scientists @ prosciediting.com